1. Field of the Invention
The present invention relates generally to a contact region for semiconductor device and more particularly to a minimum contact resistance semiconductor device contact region. The present invention also relates to a method for manufacturing a semiconductor device comprising a contact region having reduced contact resistance.
2. Description of the Background Art
In the manufacture of a semiconductor integrated circuit, when a transistor or the like is formed on the surface of a semiconductor substrate, P type or N type impurities need be diffused in the semiconductor substrate.
Diffusion of impurities comprises the step of introducing impurities shallow to the surface of the semiconductor and the step of diffusing impurities deeply in the semiconductor. The former step done by a method of introducing impurities from the surface of the semiconductor by thermal diffusion or a method of implanting atoms of impurities to the semiconductor by ion implantation. In the thermal diffusion method, impurity gas having higher concentration is transmitted from a diffusion source to a heated wafer surface and impurities are diffused to the shallow portion of the surface in a short period of time to the solid solubility. It is difficult to accurately control the impurity concentration on the wafer surface in the thermal diffusion method, and this method is used only when impurities are to be diffused deeply to higher concentration.
Meanwhile, as described in "ION IMPLANTATION" by T. E. SEIDEL pp. 219 to 265, Chapter SIX of VLSI TECHNOLOGY edited by SZE, the ion implantation is a method of ionizing such as gas including impurities, selectively taking out the required ions of the ionized gas by mass spectrometry employing an electric field/magnetic field, accelerating the ions by the electric field to irradiate the semiconductor substrate, thereby implanting the impurities into the semiconductor substrate.
When boron are introduced by ion implantation to a P.sup.- or N.sup.- silicon substrate, a P.sup.+ region is formed on the silicon substrate, and when phosphorous or arsenic ions are implanted, an N.sup.+ region is formed. The concentration of impurities can be easily controlled in the ion implantation, and the distribution of impurity concentration can be well reproduced. Therefore, this method is widely used.
In addition, Japanese Patent Publication No. 49-15377 discloses the formation of an oxide film on an exposed surface of a semiconductor substrate during a thermal diffusion process after implantation in order to prevent contamination of the impurity region formed by ion implantation and to provide electrical contact at the region where the concentration of ions is the highest. FIGS. 1A and 1B are views of a semiconductor device showing an outline of its manufacturing steps used therein. Then, referring to FIGS. 1A and 1B, a description is made of manufacturing steps of a contact portion of a conventional semiconductor device.
Referring to FIG. 1A, an oxide film 20 is formed on a main surface of a semiconductor substrate, for example, n-type Si substrate 10. Photoetching is performed on this oxide film 20 to expose a predetermined portion of the semiconductor substrate 10. Then, ions of impurities 30 such as phosphorous or boron are implanted on the exposed surface of the semiconductor substrate 10 using a residue of an oxide film 20 as a mask. As a result, an ion implanted layer 40 is provided.
Referring to FIG. 1B, a heat treatment is performed at 900.degree.-1300.degree. C. in order to activate impurities introduced by the ion implantation and to recover from a lattice defect. The reason why the impurities are activated is that the region where the impurities are implanted does not exhibit the nature as the N.sup.+ or P.sup.+ region unless they are activated. The above described lattice defect is generated by collision of ions having high energy with Si crystals during ion implantation, which causes leak current and the like.
During this heat treatment, the semiconductor substrate 10 to which ions are implanted is heated to the temperature of 900.degree. to 1300.degree. C. in the N.sup.2 gas atmosphere and exposed to O.sub.2 gas for a predetermined time period. In this processing, the exposed surface of the semiconductor substrate 10 is oxidized to form an oxide film 50 and the impurity ions are thermally diffused to form an impurity diffusion region 60. In this processing, a predetermined temperature and hour conditions such as 800.degree. C., 20 minutes are used to obtain a desired impurity concentration of the impurity diffusion region 60.
When the thus formed impurity diffusion region 60 is to be electrically connected to another active region or bonding pad and the like, the oxide film 50 is etched away and a metal wiring layer 70 is formed on the impurity diffusion region 60 as shown in FIG. 1C.
A multilayer interconnection structure is employed in order to improve the speed of operation of the circuit. A metal having high melting point has relatively large resistance, and therefore, a metal having lower melting point such as Al having lower resistance is used as the material for interconnection in the multilayer interconnection structure. However, the metal having low melting point, especially Al is melt during heat treatment at the temperature of 900.degree. to 1300.degree. C. Therefore, the above described manufacturing method can not be applied to a semiconductor device having the multilayer interconnection structure employing the metal having lower melting point such as Al.
The concentration distribution of the implanted ions in the state after implantation is shown by a solid line in FIG. 2. The ions entered the substrate lose their energy by the interaction with the atoms constituting the substrate to be in the static state, so that a distribution having a single peak such as shown in FIG. 2 is provided. The concentration distribution changes under the influence of ion diffusion by the heat treatment and the oxide film thickness formed on the other hand. After the thermal diffusion, infinite numbers of distribution profiles can be provided dependent on the manner of heat treatment. Two examples of concentration distribution are shown by dotted lines in FIG. 2. Although it is possible to provide a single peak distribution after the thermal diffusion, it is very difficult to set the temperature and atmosphere conditions to realize distribution with a single peak, since the surface of the semiconductor substrate is oxidized during thermal diffusion, as described above.
In addition, in order to perform the treatment under the condition found out, it is necessary to prepare a control apparatus capable of precisely controlling the temperature and atmosphere.
In addition, generally it is desired to reduce contact resistance between the impurity diffusion region 60 and the metal wiring 70 in the above described semiconductor device. Especially the above described contact resistance should be lower in the memory. In this case, the impurity diffusion region 60 needs to be connected to the metal wiring 70 at a maximum point of the concentration of the impurities. At this time, since it is easy to etch only the oxide film away, it is thought to bring the maximum point of the concentration to the interface between the oxide film 50 and the impurity diffusion region 60. However, since the maximum point of the concentration changes depend on the temperature and atmosphere conditions because of the above described reason, it is extremely difficult to correspond the above mentioned interface with the maximum point of the concentration.